Mentor Graphics Essay, Research Paper

Aim

To finish all facets of the exercising sing D type reversal, TTL and CMOS and to familiarise us with the HDL package which is Mentor Graphics. This package is capable of building and imitating a peculiar design.

As for this assignment 1, we are given 4 hebdomads to finish the assignment. It is mandatory to go to every lab Sessionss as there is no alternate package to utilize. Merely a certain bound of clip is given for the usage of the package and hence designing of circuit is required to be completed before go toing the lab. To give pupils a first-hand apprehension of the EDA lab and most significantly Mentor Graphics, a powerful tool in HDL engineering.

This assignment allows the pupils to understand or instead familiarise themselves with the design flow of the EDA package and to to the full research what the package is capable and powerful to make.

Last, to fix the pupils for the following assignments which uses the similar package.

Introduction & # 8211 ; D ( elay ) Flip-Flop ( What You Have to Know First! )

The D reversal is utile when a individual information spot ( 1 or 0 ) is to be stored. An extra inverter to the S-R reversal at the R input creates a D reversal. The D flip-flop shown below is a alteration of the clocked SR reversal. The D input goes straight into the S input and the complement of the D input goes to the R input.

If there is a HIGH on the D input when a clock pulsation is applied, the flip-flop SETs and shops a 1. If there is a Low on the D input when a clock pulsation is applied, the flip-flop RESETs and shops a 0. The truth table below summarizes the operations of the positive edge-triggered D reversal. As earlier, the negative edge-triggered reversal works the same except that the falling border of the clock pulsation is the triping border.

( a ) Logic diagram with NAND Gatess

( B ) Graphical symbol

InputsD CP ( CLK ) OutputsQ Q & # 8217 ; Remarks

1 1 0 SET ( shops 1 )

0 0 1 RESET ( shops a 0 )

( degree Celsius ) Passage tabular array

CP ( CLK )

D ( Input )

Q ( Output )

( vitamin D ) Wave form

Procedure for Standard, TTL and CMOS

D ( elay ) Flip-Flop ( Standard )

The circuit of a D Type reversal has already been given to us. We are required to build the given circuit utilizing Design Architect ( DA ) . The constructed circuit is shown in figure 1 printed out utilizing the lab pressman.

Next, a symbol of the circuit is created utilizing DA from the bill of fare Miscellaneous followed by Generate Symbol. The created symbol is than modified. The modified symbol is shown in figure 2.

Following, Quicksim is activated chiefly to raise forces on the constructed circuit and to Trace every bit good as to analyse the end product of the circuit through wave forms.

The saved file of the constructed circuit utilizing DA is opened in Quicksim. First, the map TRACE is used to follow PRE, CLR, CLK, D, Q, QB. After this a Trace box will look at bottom lower left of the screen. This is where the fake wave forms will apprear.

Forces is so added to each of the traced constituents except for Q and QB.

Component Value of Force

PRE 1 at clip 0

CLR 0 at clip 0 and 1 at clip 35

CLK Period 100, 50 % responsibility rhythm

D Period 160, 50 % responsibility rhythm

After coercing the constituents with the needed values, type RUN 800. The wave forms will look precisely the same as the needed wave forms printed out in figure 3. ( please note that the traced constituents are included in the wave form consequences )

As we can see clearly in figure 3, the inputs of D are copied consecutive to the end product Q. Transitions occurs at every positive-edge of the clock. Therefore the wave forms agree with the specification mentioned above.

Next, an experiment is done by altering the PRE and CLR to moo. Theoretically, an illegal end product would go on. The traced end product with the above constellation is printed in figure 4. We can see that when both PRE and CLR are low ensuing the end product of Q and QB to be high. QB is defined to be the antonym of Q. However this happens ( both are High ) due to the fact that both PRE and CLR are set to moo. Therefore it is said that the end product gives an illegal operation. This is because PRE and CLK can non be set to moo at the same clip. PRE has to be HIGH to give an end product.

The following operation done to the D reversal is to analyse the end product when the CLK and input D alterations at the same time. We do this by adding force to the CLK and D by utilizing the Stimulus in the bill of fare and so snaping on ADD CLOCK ( retrieve to cancel the old forces ) . We set the period of CLK to be 100 with 50 % responsibility rhythm and 150 is set for D. The end product wave form is printed in figure 5.

By looking at the Q end product wave form, we note that at every positive lifting border of CLK and D which in this instance happens at the same time gives an oscillated end product. Why does this go on?

We have to first understand the basic construct of Timing factors. Below is a graphical account of the clip behaviour of cell.

CLK

Input signal

State

Time Behavior of Cell

? Setup clip ( tsu ) is the minimal interval from the stabilisation of the cell input to the triping border of the clock.

? Hold clip ( Thursday ) is the minimal clip interval from the triping border of the clock to a subsequent alteration in the input to the cell.

? Propagation hold ( tw ) is the clip

interval from the triping border of the clock to the stabilisation of the new province ( cell end product ) . When it is appropriate, we distinguish low-to-high and high-to-low extension holds.

After reading through the clip behaviour of cell ( taken from Introduction to Digital Systems by Milos Ercegovac, Tomas Lang and Jaime H.Moreno ) we now can reason that the oscillation happens due to the fact that the end product can non be determined whether to put to high or low. It is set in such a manner that whenever CLK and D triggers to High at the same time, oscillation occurs ( calculate 5 ) . The deficiency of apparatus up clip is the ground why oscillation happens.

TTL

The following subdivision of the assignment takes a expression at TTL holds. The standard D reversal file which was saved in the beginning is copied into a new file called dfilp_ttl. This is done by opening the old dflip file and salvaging it, typing the way name as dflip_ttl.

Delaies are inserted by snaping on alteration value in Design Architect. Select all the Numberss beside the Gatess ( ab initio 0 ) and so alter the values. The upper figure is the Rise clip and the lower figure is the Fall clip. By default the values are in nanoseconds.

The values for the 2 Gatess are tabulated below.

Gate Rise Fall

NAND 17 15

BUF 20 6

In order for the holds to take consequence on the circuit, we have to first trip the holds by snaping on SETUP, Analysis and so snap on Delay. Trace all the constituents and type RUN 800. The end product wave form is shown in figure 6.

It is seen here that with hold the end product Q is shifted to the right. However, as marked on the wave form ( A ) as the CLK is triggered as D goes low, the end product Q should travel low. Due to the deficient apparatus clip for D, the end product Q have no pick but to travel high.

When the CLK and D occurs at the same time, invalid operation occurs at the end product. Q is non the exact complement of QB, shown in figure 7. Similar consequences are acquired as PRE and CLK goes low, shown in figure 8.

The minimal period for the circuit to work decently is found to be 34.1ns. Basically, whatever is lower than the minimal period which is besides the maximal operating frequence ( 1/34ns = 29.41Mhz ) , the circuit will non work right. The end product would be invalid. How do we happen the maximal operating frequence? 1 manner is to travel through Trial and Error. By cut downing the period until we get an invalid end product. As shown in figure 9 and figure 10 the period of CLK is reduced to 50 and 40 severally. The end product is still valid.

As we can see in figure 11, the end product is invalid because Q is non wholly the complement of QB This happens when the CLK period is set to 34ns.

Another account is through basic computation. We know that the rise clip and autumn clip hold for the NAND Gatess are 17 and 15 severally. With the aid of the diagrams below, we would hold a better apprehension.

CLK

Q

Minimal Operating Time period

For the informations to be copied to the end product, the clip taken for D to make HIGH is 17ns and to make LOW is 15ns. Adding both the clip we get 33ns. Which means that the minimal period would be 34ns. Any period lower so that, end product would be invalid.

CMOS

The circuit in TTL constellation is used. The old forces of the NAND Gatess and buffer are replaced by values as shown below. The circuit is shown in figure 12.

Gate Rise Fall

NAND 160 160

BUF 80 40

The processs are repeated as in imitating the standard D reversal in the beginning.

However, due to the fact that the Trace is ab initio in nanoseconds and hence end product wave form can non be seen clearly, the environment is changed to microseconds.

The end product wave form is shown in figure 13.

The CLK period is set to 100us.

When PRE and CLK are set to LOW, invalid end product occurs. Result shown in figure 14

When the CLK and D of CMOS alterations at the same time, oscillation happens. Figure shown in figure 15.

The maximal operating frequence is found to be 1/0.33us = 3.03Mhz shown in figure 16

Remarks and Decision

By finishing the above assignment, it has given the user an in-depth apprehension on the operation on standard TTL and CMOS. Both devices are fundamentally constructed from the standard D-flip floating-point operation constellation.

By experimenting with the 3 different configured device, we can reason that they have important similarities and differences. One of which is that similar consequences occur when PRE and CLK are set to LOW. The end product Q is non the exact complement of QB. Both Q and QB are HIGH. This is because that PRE has to be set to HIGH for an end product.

Another similarity between standard and CMOS D Flip-Flop is that when CLK and D occurs at the same time, the end product at that point oscillates. This is explained in the above timing behavioural diagram. As for the TTL, end product is invalid.

The most important difference is the hold clip. The hold for TTL is much shorter as compared to CMOS.

Time direction is really indispensable in finishing this assignment. This is because merely a particular of clip is allocated for each pupil to utilize the accredited Mentor Graphics. Furthermore, it gives pupils an in deepness apprehension of the operation, features of the D Flip-Flop, TTL and CMOS and constellations.

It is indispensable to take this given chance to get the hang the package as to help us in finishing 2nd assignment.